This patent application claims priority based on a Japanese patent applications, H10-258219 filed on Sep. 11, 1998 and H11-218235 filed on Jul. 30, 1999, the contents of which are incorporated herein by reference.
The present invention relates to a waveform generator capable of generating an arbitrary waveform, and more specifically to a waveform generator capable of generating an arbitrary waveform having a short time resolution.
In order to test a device such as an LSI, an arbitrary waveform generator capable of generating arbitrary waveforms is necessary.
FIGS. 1 and 2 show examples of conventional arbitrary waveform generators. FIG. 1 is a block diagram of a conventional arbitrary generator 200. FIG. 2 is a circuit diagram of a waveform generation circuit from a conventional arbitrary waveform generator.
The arbitrary waveform generator 200 is comprised of a digital signal processor (DSP) 202 having a memory, a waveform memory 204 for storing data for generating output waveforms, a full-scale digital to analog converter (full-scale DAC) 205, an off-set digital to analog converter (off-set DAC) 206, a waveform generation digital to analog converter (waveform generation DAC) 208 for generating an arbitrary waveform, a low-pass filter (LPF) 210, an amplifier 212 and a clock control unit 214. The waveform memory 204, the full-scale DAC 205 and the off-set DAC 206 are connected to the DSP 202 respectively. The waveform generation DAC 208 is connected to the waveform memory 204. The LPF 210 is connected to the waveform generation DAC 208 and the amplifier 212 is couple to the LPF 210.
The full-scale DAC 205 serves to determine the output voltage value on the basis of a digital value stored in the waveform memory 204. The output signal from the full-scale DAC 205 is output to the waveform generation DAC 208.
The off-set DAC 206 serves to adjust the output voltage value to zero when the signal value stored in the waveform memory 204 is a xe2x80x9c0xe2x80x9d code. The output signal from the off-set DAC 206 is output to the amplifier 212. The clock control unit 214 serves to synchronize the waveform generator 200.
Referring to FIG. 2, the waveform generation DAC 208 comprises 5 current sources 221, 222, . . . to 225, with each capable of outputting predetermined current values. The current switches 231, 232, . . . to 235 are held in communication with each other through an output line. Each of the current sources 221, 222, . . . to 225 is cascaded to each of the respective current switches 231, 232, . . . to 235. One end of the output line is connected to the ground through a resistance 241 and the other end of the output line is connected to an output terminal.
Each of the respective current sources has an ability to output a current half of the previous current sources value. For example, the current source 221 is capable of outputting current with a value of I, while current source 222 is capable of outputting current of value I/2. It follows that current sources 223, 224 and 225 are capable of outputting current with values of I/4, I/8 and I/16 respectively. This means that the current switch 231 is the most significant bit (MSB) and the current switch 235 is the least significant bit (LSB). The current switches 231, 232, . . . to 235 are switched on and off by the input data from the waveform memory 204. For example, when the input data from the waveform memory 204 is xe2x80x9c00101xe2x80x9d, the currect switches 233 and 235 are switched on to output current having a current value of (I/4+I/16). The current is output to the output terminal via the resistance 241 to give an output signal (I/4+I/16)xc3x97R. The full-scale DAC 205 determines the actual values of the current value I.
The waveform generator 200 can generate an arbitrary waveform by switching on and off the current switches in accordance with the input data from the waveform memory 204.
The time resolution of the waveform generated by the conventional waveform generator described above is determined by the operational speed of the current switches 231, 232, . . . to 235. The current switches 231, 232, . . . to 235 are operated at 1 GHz frequency. This means that the conventional waveform generator can generate a waveform having a time resolution as short as 1 nsec.
The conventional waveform generator therefore cannot generate a waveform having a shorter time resolution than 1 nsec although there are applications where this may be required. For example, it is necessary to use an arbitrary waveform having a time resolution as short as 8 GHz sampling/sec to test an AC characteristic of a device for high speed interface such as a 1 GHz Ethernet (registered trademark). The conventional waveform generator is therefore unsuitable for this application as it cannot generate an arbitrary waveform with a time resolution of more than 1 GHz due to the speed limitation of the current switches 231, 232, . . . to 235.
It is an object of the present invention to provide a waveform generator capable of generating an arbitrary waveform with an adequately short time resolution to solve problems similar to that described above. It is another object of the present invention to provide a semiconductor testing device and a semiconductor device both including the waveform generator.
The waveform generator comprises an input terminal to which an input signal is input; a delay unit having a plurality of delay means for delaying propagation of the input signal to output a delayed input signal, the delay means being cascaded with each other; a processing unit having a plurality of processing means, each of the processing means outputting an output signal based on each of the delayed input signal input thereto; and a composing unit for composing the output signals from each of the processing means of the processing unit to generate a waveform.
The waveform generator may also comprise a plurality of the delay units connected to the input terminal in parallel relationship with each other; and a plurality of the processing units correspondingly provided to each of the plurality of delay units. The composing unit adds the output signals from each of the processing means to give a sum total value and generates the waveform on the basis of this total value. The processing unit comprises processing means into which the input signal is fed to the input terminal.
The waveform generator may further comprise a plurality of memory for storing data for generating the waveform, each of which is connected to each of the respective plurality of processing means. Each of the processing means outputs the output signal on the basis of the data for generating the waveform stored in each of the memory.
The processing means may either directly output the delayed input signal or outputs after reversing the delayed input signal as the output signal on the basis of the data for generating the waveform. The memory of the waveform generator may store a plurality of data for generating the waveform, and the processing means outputs the output signal on the basis of the plurality of data stored in the memory. The result is the waveform generated comprises a longer period wave than the input signal.
The waveform generator may also contain a data control unit for controlling the plurality of data for generating the waveform to be output at a predetermined interval and the processing means outputting the output signal on the basis of the data for generating the waveform output by the data control unit. The delay unit may include first and last delay means each having an input and an output, the input of the first delay means being connected to the input terminal, and the output of the last delay means being connected to the input of the first delay means. The processing means may output the output signal on the basis of the input signal and the data for generating the waveform stored in the memory means. The composing unit generates a pulse having a predetermined pulse width as the waveform on the basis of the output signal.
The processing means may output the output signal on the basis of the input signal, the data for generating the waveform stored in the memory means, and the delayed input signal delayed for a predetermined duration. The composing unit may generate a pulse having a predetermined pulse width as the waveform on the basis of the output signal. Each of the processing means may output current with the same value as the output signal.
The composing unit may compose the output signal from each of the processing means to generate the waveform having a value corresponding to the number of the processing means. Each of the processing means comprises a current supply circuit for supplying current on the basis of the output signal and a reverse signal of the output signal. The waveform generator may further contain a minute delay element provided between the input terminal and the first delay means, the minute delay element having a smaller delay duration than that of the delay means. Additionally it may contain a plurality of minute delay elements each provided between the input terminal and the first delay means of each of the delay units, the minute delay element having a smaller delay duration than that of the delay means.
The semiconductor testing device may comprise a waveform generator for generating on the basis of an input signal, a test signal to be input to the device under test; a signal input and output unit for supplying the test signal to the device under test and accepting a device output signal from the device under test on the basis of the test signal; and a testing unit for testing the quality of the device under test on the basis of the device output signal accepted by the signal input and output unit. The waveform generator may comprise an input terminal to which an input signal is input; a delay unit having a plurality of delay means for delaying propagation of the input signal to output a delayed input signal, the delay means being cascaded with each other; a processing unit having a plurality of processing means, each of the processing means outputting an output signal based on each of the delayed input signals thereto; and a composing unit for composing the output signals from each of the processing means of the processing unit to generate a waveform of the test signal.
The waveform generator comprises; a plurality of the delay units connected to the input terminal in parallel relationship with each other; and a plurality of the processing units correspondingly provided to each of the plurality of delay units. The semiconductor testing device may have a composing unit which adds the output signals from each of the processing means to give a summed total value, and generates the waveform on the basis of this total value. The waveform generator may further comprise a plurality of memory for storing data for generating the waveform, each of the plurality of memory respectively being connected to each of the plurality of processing means, each of the processing means outputting the output signal on the basis of the data for generating the waveform stored in each of the memory.
The semiconductor device having self-testing ability comprises a device circuit constructed to actualize a predetermined function; a waveform generation circuit for generating a test signal to be input to the device circuit; and a signal output unit for outputting a device output signal from the device circuit on the basis of the test signal, to the external of the semiconductor device. The waveform generation circuit may comprise a delay !unit having a plurality of delay means for delaying the propagation of an input signal to output a delayed input signal, the delay means being cascaded with each other; a processing unit having a plurality of processing means, each of the processing means outputting an output signal based on each of the delayed input signals input thereto; and a composing unit for composing the output signals from each of the processing means of the processing unit to generate a waveform of the test signal.
The waveform generation circuit may comprise; a plurality of the delay units connected in parallel relationship with each other; and a plurality of the processing units correspondingly provided to each of the plurality of delay units. The composing unit adds the output signals from each of the processing means to give a sum total value and generates the waveform on the basis of this total value. The waveform generation circuit may further comprise a plurality of memory for storing data for generating the waveform, where each of the plurality of memory is connected to each of the plurality of processing means, and each of the processing means outputting the output signal on the basis of the data for generating the waveform stored in each of the memory.